LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY mux3x32 IS
	PORT
	(
		data0x		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		data1x		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		data2x		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		sel		: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
		result		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
	);
END mux3x32;


ARCHITECTURE SYN OF mux3x32 IS
begin
	with sel select
		result <= data0x when "00",
				  data1x when "01", 
				  data2x when others;		
END SYN;

